Computer Hardware

Covers computer memory, processors, storage, and hardware architecture — building toward GPU compute and CUDA kernels for ML workloads.

dram-overview — What DRAM is, memory hierarchy, DIMM packaging, DDR5 key metrics
dram-memory-cell — 1T1C cell structure, sense amplifiers, and on-die ECC
dram-bank-die-structure — 32 banks (65,536 × 8,192 cells each), bank-group layout, and bank independence
dram-address-multiplexing — 31-bit address breakdown; RAS/CAS time-multiplexing over the CA bus
dram-read-write-refresh — read, write, and refresh operation sequences (REFab vs REFsb)
dram-row-hits-and-latency — RAS/CAS, row hit vs. miss, latency metrics (tRP, tRCD, tCL, tRAS)
dram-burst-buffer — 128-bit burst buffer, burst length 16, 16× multiplexer bandwidth improvement
dram-subarrays — 1,024 × 1,024 subarray structure and intermediate sense amplifier placement

Foundations

cpu-architecture-overview — the 10-layer abstraction stack from transistor to application; map of the CPU pages
logic-gates-and-transistors — MOSFET, CMOS NAND, standard cell library, flip-flops, combinational vs sequential
cpu-clocks — quartz oscillator, PLL (VCO + divider + PFD + loop filter), fractional-N, H-tree distribution, DVFS, critical path
rtl-to-silicon — RTL → synthesis → place-and-route → STA → DRC/LVS → GDSII → tape-out

Architecture & implementation

cpu-isa — RISC vs CISC, ARM64 vs x86-64, RISC-V, the ISA contract; why fixed-width matters
cpu-microarchitecture — pipeline, superscalar, OoO, register rename, branch predictor, speculation
cpu-pipeline — 5-stage classic pipeline, hazards (RAW/control/structural), forwarding, depth trade-offs, OoO
cpu-decoder — RISC combinational decode, CISC pre-decode + PLA + microcode, 8086 group decode ROM

Specific implementations

cpu-m1-soc — Apple M1 system-on-chip die layout (Firestorm + Icestorm clusters, GPU, NPU, unified memory)
cpu-m1-firestorm-core — M1 high-performance core: front end (8-wide decode), back end (~630-entry ROB), execution units
cpu-6502 — MOS 6502 die analysis; visual6502 transistor-level simulator; pedagogical decoder topology

Variants

cpu-types — CPU vs MCU vs SoC vs GPU vs NPU/TPU vs ASIC vs FPGA — the flexibility ↔ efficiency spectrum

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