DRAM Read, Write, and Refresh Operations

Summary: Every DRAM operation — read, write, or refresh — is driven by a 31-bit address decoded into a bank, row, and column, with the row-open step (ACT command) being the most expensive and shared across all three; DDR5 adds per-bank refresh (REFsb) to reduce the performance penalty of mandatory refresh cycles.

Read operation

See dram-address-multiplexing (RAS and CAS phases) for how 31-bit logical address is used to access a byte (8 bits) of data in memory.

1. Bank select (5 bits) — PRE command:

   1. Deactivate all 65,536 wordlines (close all rows, including current open) in the selected bank → isolate all capacitors.
   2. Precharge circuit drives all 8,192 bitlines and their complements to Vcc/2 = 0.55 V (the sense amplifier detection reference for DDR5).

2. Row open (16 bits) — ACT command:

   1. Row decoder activates 1 wordline → all 8,192 capacitors in that row connect to their bitlines simultaneously → each capacitor causes a ~150 mV shift on its bitline → sense amplifiers latch, driving each bitline to 0 V or 1.1 V.

   2. The row is now open.

   Reads are destructive, necessitating read-triggered refreshes

   Charge-sharing partially depletes the capacitor regardless of its stored value. On every read operation, The sense amplifier latch drives the bitline back to 0 V or Vcc through the still-open access transistor, which restores the capacitor. Without this automatic restoration, data would be permanently lost after every read.

   See: Sense amplifiers section (charge sharing and amplification)

3. Column select (10 bits) — RD command: Column multiplexer connects 8 of the 8,192 open bitlines to the read driver → 8 bits sent to the CPU via the chip’s 8 data wires.

Gotcha — all 8,192 columns activate regardless of how many you read

Opening a wordline physically connects every capacitor in that row to its bitline simultaneously. The column multiplexer selects which amplified bitlines to route to the data bus — it does not control which columns activate. All 8,192 sense amplifiers do their work no matter how many columns you intend to read.

Write operation

Steps 1 and 2 are identical to read (PRE + ACT: bank select, precharge, row open, sense-amplifier latch). Step 3 differs:

3. Column select (10 bits) — WR command: Column multiplexer connects 8 bitlines to the write driver. The Write Enable (WE) signal distinguishes this path from a read. The write driver is significantly stronger than the sense amplifiers — it overrides them, forcing the 8 selected bitlines to 0 V or 1.1 V per the CPU’s data. The 8 connected capacitors are charged or discharged accordingly.
   • Write-triggered refresh: the write driver also fully restores those 8 capacitors to their target voltage.

Refresh operation

Capacitors leak charge through the access transistor’s imperfect isolation over time. A logic-1 capacitor (1.1 V) will eventually decay below the 0.55 V detection threshold and be misread as 0. Refresh prevents this.

REFab — All-Bank Refresh (DDR4 and DDR5)

Refreshes one row simultaneously across all 32 banks. The entire DRAM is unavailable for read/write during tRFCab.

Steps:

1. Deactivate all wordlines (all 32 banks) → isolate all capacitors
2. Precharge all 8,192 bitlines per bank to 0.55 V
3. Activate each of the 65,536 rows sequentially (~50 ns per row, ~3 ms per bank)
   • Sense amplifiers restore all 8,192 capacitors per row to 0 V or 1.1 V

REFsb — Same-Bank Refresh (DDR5 new)

Refreshes one row in the same bank position (i.e. 1 of the 4 banks) across all 8 bank groups simultaneously, leaving the other 3 banks per group accessible for read/write. Shorter blackout window.

Refresh type	Command	Scope	Typical duration (16 Gb die)	Banks blocked
All-bank	REFab	All 32 banks	tRFCab ≈ 295 ns	All 32
Same-bank	REFsb	8 banks (1 per group)	tRFCsb ≈ 190–220 ns	8 of 32

Refresh scheduling

• The memory controller issues REF commands at average intervals of tREFI ≈ 7.8 µs
• This guarantees all 65,536 rows in every bank are refreshed within the 64 ms retention window (worst-case capacitor charge retention at normal operating temperature)
• At elevated temperatures (>85°C), cells leak faster; DDR5 tightens the refresh interval to maintain data integrity

Charge and leakage

DDR5 Vcc = 1.1 V. Logic-1 capacitors are charged to ~1.1 V; logic-0 capacitors are at 0 V. The 64 ms refresh window is set below the worst-case time for a fully-charged 1.1 V capacitor to leak below the 0.55 V detection threshold.

Earlier generations operated at higher Vcc (DDR2: 1.8 V, DDR4: 1.2 V), providing a larger voltage margin but consuming more power. DDR5’s lower voltage demands tighter refresh discipline.

Concurrent operation across chips

Within a memory sub-channel, all 4 DRAM chips receive the same 31-bit address and command signals simultaneously. Each chip independently accesses the same logical bank/row/column in its own die and drives its own 8 data wires. A single read or write command therefore transfers 4 × 8 = 32 bits in parallel across the sub-channel.

Images: Two independent 32-bit memory sub-channels A and B, each with its own CA bus

Images: 32-bit sub-channels data (DQ) lines wired in parallel across four ×8 chips (i.e. 8-bit)

Hence each chip has 8-bit read/write only

See also

• dram-address-multiplexing — full 31-bit address breakdown and RAS/CAS multiplexing mechanism with diagrams
• dram-memory-cell — 1T1C cell structure, charge-sharing physics, and sense amplifier circuit
• dram-bank-die-structure — physical layout of the 32 banks being addressed and why bank independence matters
• dram-row-hits-and-latency — how skipping the row-open step (row hit) saves ~80 cycles; REFsb bank-group parallelism
• dram-burst-buffer — how the column-select step is further optimised with a burst buffer

Sources

• Branch Education — How Does Computer Memory Work?
• Wikipedia — DDR5 SDRAM
• Mean9Park — Basic DRAM Configuration and Operation
• Micron — DDR5 SDRAM New Features White Paper
• ElectricalFundaBlog — DDR5 SDRAM Features and Architecture