Summary: A DDR5 die organises its 17 billion 1T1C cells into 32 fully independent banks (8 bank groups × 4 banks each), where each bank is a 65,536 × 8,192 grid of cells with its own dedicated row decoder, bitlines, and sense amplifiers — independence that enables bank-group interleaving and parallel refresh scheduling.
Bank grid
Each bank is a 2D array of 1T1C cells:
| Dimension | Value |
|---|---|
| Rows (wordlines) | 65,536 |
| Columns (bitlines) | 8,192 |
| Cells per bank | 65,536 × 8,192 = 536,870,912 |
Numbers above are for a 16 Gb DDR5 die with a ×8 chip. Higher-density dies scale row or column counts accordingly.
Die structure
| Level | Count | Notes |
|---|---|---|
| Bank groups | 8 | Doubled from DDR4’s 4; enables finer refresh scheduling and bank-group interleaving |
| Banks per group | 4 | |
| Total banks | 32 | DDR4 had 16 |
| Total cells | 32 × 536,870,912 = 17,179,869,184 | 17,179,869,184 bits ÷ 8 = ~2 GB ✓ |
TODO: Functional architecture diagram — Address Input (31-bit) → Bank Group/Bank Control (×5) → Row Decoder (×16) → 65,536 rows → Sense Amplifiers (×8,192) → Column Multiplexer (×10) → Read Driver / Write Driver → ×8 Data Wires. Shows 17 billion memory cells total.
TODO: Bank grid diagram — 8,192 columns × 65,536 rows shown as a 2D cell array, with 8 active cells highlighted in one row, Column Multiplexer at the bottom, and ×8 data wires to memory channel/CPU.
Bank independence
Every bank has its own independent wordlines, bitlines, row decoder, and sense amplifiers — banks share no internal circuitry. This matters for two reasons:
- Bank-group interleaving: While one bank is in a row-open or precharge state, another bank (especially in a different bank group) can be serviced immediately. The memory controller pipelines commands across banks to hide latency.
- Parallel refresh scheduling: DDR5’s REFsb (same-bank refresh) refreshes one row across all 8 bank groups simultaneously, leaving the other 3 banks per group accessible. Bank independence makes this possible without data corruption — see dram-read-write-refresh.
Each bank is further subdivided into 1,024 × 1,024 subarrays with intermediate sense amplifiers to reduce bitline length and power — see dram-subarrays.
See also
- dram-memory-cell — 1T1C cell structure, charge-sharing physics, and sense amplifier circuit
- dram-address-multiplexing — how the 31-bit address selects a specific bank, row, and column
- dram-read-write-refresh — how bank independence enables REFsb parallel refresh
- dram-row-hits-and-latency — bank-group interleaving and row-hit optimisation
- dram-subarrays — subarray subdivision within each bank
Sources
- Branch Education — How Does Computer Memory Work?
- Micron — DDR5 SDRAM New Features White Paper
- StoredBits — Understanding the DRAM: How does Computer Memory Work?