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DRAM Memory Cell (1T1C)

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Summary: Each DRAM memory cell is a 1T1C structure — 1 access Transistor gating 1 storage Capacitor — where a sense amplifier at the bottom of each bitline detects the ~150 mV charge-sharing signal and amplifies it to full logic swing (logic 0 or 1), simultaneously refreshing the destructively-read capacitor.

The 1T1C cell

ComponentRole
Trench capacitorStores 1 bit:
- fully charged (~1.1 V for DDR5, = Vcc) = logic 1;
- fully discharged (0 V) = logic 0
WordlineHorizontal wire (i.e. 65,536 rows in 1 bank)
→ applying voltage to the transistor gate turns it ON
→ “connects” all 8,192 capacitor on that bank’s row to their bitlines
Access transistor (NMOS)Gates access to the capacitor — not for computation, purely for capacitor isolation
BitlineVertical wire (i.e. 8,192 columns)
→ data path between the transistor channel and the sense amplifier / drivers
→ Only 1 of the 65,536 capacitors (rows in that column) may be active (“connected”) at a time

How the transistor gates access

Only 1 wordline is active at a time

All 8,192 capacitors in a bank are always connected to their bitlines (columns), but only 1 wordline (row) is active at a time

  • Wordline (row) voltage high → NMOS channel opens → capacitor connects to bitline (column) → read or write possible
  • Wordline (row) voltage low → NMOS channel closes → capacitor isolated → holds previously set 0/1 charge

The transistor performs no logic. Its sole purpose is to gate access to the capacitor — the minimum possible addressable storage circuit.

Trench capacitor (holds 1 bit): Cylindrical structure etched vertically (below the transistor) into the silicon substrate to maximise capacitance per unit of die footprint. A modern DRAM trench capacitor holds ~10–20 fF. This is small enough that connecting it to the long bitline causes only a ~150 mV voltage shift — requiring dedicated (sense) amplification.

Sense amplifiers

Each bitline connects to a sense amplifier (SA) at the bottom of its subarray. The SA must detect a ~150 mV shift—from a single capacitor (1 active wordline)—and drive the bitline to full logic 0/1 swing (0 V or Vcc = 1.1 V for DDR5).

Pre-charge

Before each row open, a pre-charge circuit — three NMOS transistors: two pre-charge transistors driving each bitline rail, and one equaliser transistor connecting BL to /BL — drives both bitline and its complement (/BL) to Vcc/2 = 0.55 V. This midpoint is the SA’s detection reference.

Charge sharing

When the wordline activates, the cell capacitor charge-shares with the bitline:

Cell stateEffect on BLVoltage shift
Logic 1 (charged, ~1.1 V)Pushes BL above 0.55 V+~150 mV
Logic 0 (discharged, 0 V)Pulls BL below 0.55 V−~150 mV

The differential between BL and /BL (still at 0.55 V) is only ~150 mV — too small for digital logic to use directly.

Amplification (latch phase)

The SA is a regenerative cross-coupled latch — four transistors (two NMOS, two PMOS) in a cross-coupled inverter pair. Two enable signals trigger the latch after charge sharing:

  • SAN (sense amplifier n-type): connects the latch bottom to GND
  • SAP (sense amplifier p-type): connects the latch top to Vcc

Once SAN and SAP are asserted, positive feedback drives BL and /BL to opposite rails: the side marginally above 0.55 V goes to 1.1 V; the other goes to 0 V. Full 1.1 V swing is restored in nanoseconds.

Read-triggered refresh: The latch drives BL back to 0 V or 1.1 V. Through the still-open access transistor, this restores the capacitor to full charge. Reading a row refreshes all 8,192 of its cells automatically — critical because the read is destructive: charge-sharing partially depletes the capacitor regardless of its stored value. Without SA restoration, data would be lost after every read.

On-Die ECC review

DDR5 mandates on-die ECC (ODECC) in every chip — a first for mainstream DRAM. As cells shrink with each process generation, transient single-bit errors (from particle strikes, thermal noise, and row hammer disturbance) become more frequent; ODECC corrects these before they reach the CPU.

Mechanism:

FieldBitsRole
Data128Actual payload read from the array
Parity8Syndrome computed over the 128 data bits
Codeword136Total bits fetched internally per chip per read
  • During every read, all 136 bits are fetched from the array (128 data + 8 parity)
  • A syndrome is computed; any single-bit error is identified and corrected inside the chip
  • The CPU receives corrected 128-bit data — errors are completely transparent/invisible to the OS and applications
  • Double-bit errors are detected but not corrected

What ODECC is not: It operates on the 128-bit internal data path, not the 8-bit external ×8 interface. Errors are not logged or reported upward. It is separate from system-level ECC DIMMs, which add extra chips and a wider bus to detect and report errors at the DIMM level, visible to the OS.

See also

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