Summary: DRAM addresses are time-multiplexed over a narrow Command/Address bus in two phases — RAS (bank + row) carried by the ACT command, and CAS (column) carried by the RD/WR command — allowing a 31-bit logical address to be transmitted without a 31-bit-wide physical bus.
The 31-bit logical address
Each DRAM command is associated with a 31-bit address decoded in three phases:
| Phase | Bits | Selects | Size |
|---|---|---|---|
| Bank select | 5 | 1 of 32 banks (8 bank groups × 4 banks each) - 3-bit bank group (1–8) - 2-bit bank number in group (1–4) | 2⁵ = 32 banks |
| Row Address Strobe ( RAS) | 16 | 1 of 65,536 wordlines (rows) - 16-bit row number (1 of 65,536 rows) | 2¹⁶ = 65,536 rows |
| Column Address Strobe ( CAS) | 10 | No burst buffer: 8 of 8,192 bitlines (columns/capacitors) - 10-bit column number (8 contiguous of 8,192 columns) With burst buffer: 1 of 1,024 burst positions (each = 8 cols) - 6-bit multiplexer (select 11 of 64 contiguous groups of 128 bitlines) - 4-bit burst length (select 1 of 16 eight-bit segments within 128-bit burst buffer) | 2¹⁰ = 1,024 positions |
Total: 5 + 16 + 10 = 31 bits. Each column position maps to 8 bitlines → 8 bits per chip → 32 bits across the 4-chip sub-channel.
Numbers above are for a 16 Gb (2 GB) die. Higher-density dies use more row or column bits.
Address multiplexing
The Command/Address (CA) bus is narrower than 31 bits. The RAS and CAS phases are sent as separate transfers on the same physical address pins:
ACTcommand carries theRASphase: 3-bit bank group, 2-bit bank number, 16-bit row numberRD/WRcommand carries theCASphase: 10-bit column number
This is why you see two distinct timing parameters in DRAM specs: tRCD (the gap between ACT and RD/WR) and tCL (the latency from RD to first data). See dram-row-hits-and-latency.
RAS phase — bank and row selection
Bank selection (5 bits)
Image: Bank selection 5 bits
Row decoder selection and activation (16 bits)
2 Images: Row decoder selection ( 16 bits) and activation
Activating a row opens all 8,192 capacitors in that wordline simultaneously — every sense amplifier on the bitline column latches its ~150 mV charge-sharing signal to full 0 V / 1.1 V swing. See dram-memory-cell for the sense amplifier circuit detail.
CAS phase — 8-column selection
Column multiplexer selection and 8-column activation (10 bits)
3 Images: Column multiplexer selection ( 10 bits) and activation of 8-columns
The 10-bit column address selects 1 of 1,024 burst positions, each spanning 8 consecutive bitlines. The column multiplexer routes those 8 amplified bitlines to the chip’s 8 data wires.
Outcome: 8-bit data access (1 cell per bitline)
Image: 8 active (connected) memory cells
See also
- dram-bank-die-structure — physical layout of the 32 banks, rows, and columns being addressed
- dram-read-write-refresh — how ACT + RD/WR/REF commands use this address breakdown in full operation sequences
- dram-row-hits-and-latency — tRCD, tCL, and the cost of issuing ACT before every column access
- dram-memory-cell — sense amplifier circuit triggered by the row activation step
Sources
- Branch Education — How Does Computer Memory Work?
- Wikipedia — DDR5 SDRAM
- Mean9Park — Basic DRAM Configuration and Operation
- Micron — DDR5 SDRAM New Features White Paper
Footnotes
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must be 128 contiguous bitlines ↩